general description the ds4302 is a 5-bit digital-to-analog converter (dac) with three programmable digital outputs. the ds4302 communicates through a 2-wire, smbus -compatible, serial interface. the tiny 8-pin ?op package is ideal for use in space-constrained applications. applications ccfl backlight brightness control power-supply calibration features ? so package is a drop-in replacement for the mps1251 and mps1252 ? single 5-bit dac (32 steps) ? 0v to 2v and 0v to 1.9v versions ? three programmable digital outputs ? smbus-compatible serial interface ? 4.5v to 5.5v supply voltage range ? 8-pin so and 8-pin sop packages ? industrial temperature range: -40c to +85c ds4302 2-wire, 5-bit dac with three digital outputs ______________________________________________ maxim integrated products 1 top view p1 p2 gnd 1 2 8 7 v cc p0 sda v out scl so/ sop 3 4 6 5 ds4302 pin configuration ordering information rev 1; 6/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. add ?t&r?for tape-and-reel orders. * contact factory for availability. smbus is a trademark of intel corp. part v out range top brand pin- package ds4302z-020 0v to 2.0v 4302b 8 so ds4302z-019* 0v to 1.9v 4302a 8 so ds4302u-020 0v to 2.0v 4302b 8 ?op ds4302u-019* 0v to 1.9v 4302a 8 ?op pin description pin name function 1 scl serial clock input. 2-wire clock input. 2 sda serial data input/output. bidirectional, 2-wire data pin. 3v out dac output voltage 4 gnd ground 5p2 6p1 7p0 programmable digital output 8v cc power-supply input
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs ds4302 part number table notes: see the ds4302 quickview data sheet for further information on this product family or download the ds4302 full data sheet (pdf, 544kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number notes free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds4302z-020+ 20kohms soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+2 * 0c to +70c rohs/lead-free: yes materials analysis ds4302z-020+t&r 20kohms soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+2 * 0c to +70c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y
ds4302 2-wire, 5-bit dac with three digital outputs 2 _____________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -40? to +85?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , sda, and scl pins relative to ground.............................................-0.5v to +6.0v operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +125? soldering temperature.....see ipc/jedec j-std-020a specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 4.5 5.5 v input logic 1 (sda, scl) v ih 2.0 v cc + 0.3 v input logic 0 (sda, scl) v il gnd - 0.3 0.8 v parameter symbol conditions min typ max units standby current i stby (notes 2, 3) 200 300 ? input leakage i l (note 4) -1.0 +1.0 a 3ma sink current 0.0 0.4 sda low-level output voltage v ol1 6ma sink current 0.0 0.6 v p0, p1, p2 low-level output voltage v ol2 (note 1) 4ma sink +0.4v v p0, p1, p2 high-level output voltage v oh (note 1) 4ma source v cc - 0.4v v v out maximum level (-020) v cc = 5.0v, data = 00000xxx (note 3) 1.925 2.0 2.075 v v out minimum level (-020) v cc = 5.0v, data = 11111xxx 0.0 0.05 0.1 v v out maximum level (-019) v cc = 5.0v, data = 00000xxx (note 3) 1.825 1.9 1.975 v v out minimum level (-019) v cc = 5.0v, data = 11111xxx 0.0 0.05 0.1 v power-on reset 1.7 v settling time 10 ? d/a output levels 32 steps dc electrical characteristics (v cc = +4.5v to 5.5v, t a = -40? to +85?.) x = don? care.
ds4302 2-wire, 5-bit dac with three digital outputs _____________________________________________________________________ 3 parameter symbol conditions min typ max units scl clock frequency f scl 0 400 khz bus free time between stop and start conditions t buf 1.3 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 5) 20 + 0.1c b 300 ns sda and scl fall time t f (note 5) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 5) 400 pf ac electrical characteristics (figure 3) (v cc = +4.5v to 5.5v, t a = -40? to +85?, timing referenced to v il(max) and v ih(min) .) note 1: all voltages referenced to ground. note 2: i stby specified for the inactive state measured with sda = scl = v cc and with v out , p0, p1, and p2 floating. note 3: no load on v out . note 4: the ds4302 will not obstruct the sda and scl lines if v cc is switched off as long as the voltages applied to these inputs does not violate their min and max input-voltage levels. note 5: c b ?otal capacitance of one bus line in picofarads.
ds4302 2-wire, 5-bit dac with three digital outputs 4 _____________________________________________________________________ t ypical operating characteristics (v cc = +5.0v, t a = +25?.) standby supply current vs. supply voltge ds4302 toc01 supply voltage (v) standby supply current ( a) 5.25 5.00 4.75 50 100 150 200 250 300 0 4.50 5.50 outputs unloaded sda = scl = v cc standby supply current vs. temperature ds4302 toc02 temperature ( c) standby supply current ( a) 20 40 60 0 -20 50 100 150 200 250 300 0 -40 80 outputs unloaded sda = scl = v cc = 5.0v supply current vs. scl frequency ds4302 toc03 scl frequency (khz) supply current ( a) 300 200 100 50 100 150 200 250 300 0 0400 outputs unloaded sda = v cc v out vs. dac setting ds4302 toc04 dac setting (dec) v out (v) 30 25 20 15 10 5 0.5 1.0 1.5 2.0 0 0 ds4302-020 version v out vs. supply voltage ds4302 toc05 supply voltage (v) v out (v) 5.25 5.00 4.75 1.95 2.00 2.05 2.10 1.90 4.50 5.50 v cc = sda = scl v out percent change from +25 c vs. temperature ds4302 toc06 temperature ( c) v out percent change (%) 80 60 40 20 0 -20 -0.5 0 0.5 1.0 -1.0 -40 v cc = sda = scl
ds4302 2-wire, 5-bit dac with three digital outputs _____________________________________________________________________ 5 functional diagram 2-wire interface gnd 5-bit dac v out bandgap reference scl sda msb lsb data byte register dac value p0 p2 p1 p0 v cc v cc output cell p1 p2 v cc output cell output cell buffer ds4302
ds4302 detailed description the ds4302 contains a 5-bit dac and three programma- ble digital outputs. the dac setting and the pro- grammed output levels are contained in a 1-byte data word that defaults to 00h on power-up (see figure 1 for data byte configuration). the upper 5 msbits of the byte set the dac and control the voltage produced on v out . a setting of 1111 1xxx sets the minimum output voltage from the dac while a setting of 0000 0xxx sets the maxi- mum output voltage from the dac. the three lsbits of the data byte control the three output pins, p0, p1, and p2. setting any of these control bits to a 0 pulls the corre- sponding outputs low and setting the bits to a 1 pulls the outputs high. the ds4302 communicates through a 2-wire (smbus- compatible) digital interface and has a 2-wire address of 58h. write and read operations are used to access the dac and output settings. each operation begins with a 2-wire start condition, consists of three bytes, and ends with a 2-wire stop condition (see figure 2). using the write operation, the 2-wire master can program the 5-bit dac to adjust the voltage on vout and set the level of the three output pins: p0, p1, and p2. the read operation is used to recall the programmed settings. 2-wire definitions the following terminology is commonly used to describe 2-wire data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, start, and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle, it initiates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 3 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 3 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 3). data is shifted into the device during the rising edge of the scl. 2-wire, 5-bit dac with three digital outputs 6 _____________________________________________________________________ data byte msb dac value p0 p2 p1 figure 1. data byte configuration figure 2. 2-wire communication examples s p a start 8-bits address or data stop ack white boxes indicate the master is controlling sda shaded boxes indicate the slave is controlling sda write a single byte aah read a single byte 00h 59h 58h communications key s xxxxxxxx 01011000 a data byte a p notes: 1) all bytes are sent most significant bit first. 2) the first byte sent after a start condition is always the slave address followed by the read/write bit. 0000 1111 s 01011001 a a data byte a p 0000 0000 a
bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 3) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack): an acknowledgement (ack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. for tim- ing, see figure 3. an ack is the acknowledgement that the device is properly receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must ack the last byte read to termi- nated communication so the slave returns control of sda to the master. slave address and the r/ w bit: each slave on the 2-wire bus responds to a slave addressing byte sent immediately following a start condition. the slave address byte contains the slave address and the r/ w bit. the slave address (see figure 4) is the most signifi- cant 7 bits and the r/ w bit is the least significant bit. the ds4302? slave address is 0101100x (binary), where x is the r/ w bit. if the r/ w bit is zero (01011000), the master will write data to the slave. if the r/w is a one (01011001), the master will read data from the slave. memory address: during a 2-wire write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is the second byte transmitted during a write or read operation following the slave address byte (r/ w =0). for a write operation, the mem- ory address is 10101010 (aah) and for a read opera- tion, the memory address is 00000000 (00h). ds4302 2-wire, 5-bit dac with three digital outputs _____________________________________________________________________ 7 7-bit slave address most significant bit determines read or write r/w 0 0 1 1 0 1 0 figure 4. slave address and the r/ w bit figure 3. 2-wire timing diagram sda scl stop note: timing is reference to v il(max) and v ih(min) . start t buf t low t r t f t su:dat t su:sta t hd:sta t su:sto t sp repeated start t hd:sta t hd:dat t high
ds4302 2-wire, 5-bit dac with three digital outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. dallas is a registered trademark of dallas semiconductor corporation. 2-wire communication writing to a slave: the master must generate a start condition, write the slave address (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgement during all byte-write opera- tions. see figure 2 for the write command example. reading from a slave: to read from the slave, the master generates a start condition, writes the slave address with r/ w = 1, receives an ack from the slave, reads a memory address of 00h from the slave, sends an ack to the slave, reads the data byte, then sends an ack to indicate the end of the transfer, and gener- ates a stop condition. see figure 2 for the read com- mand example. application information power-supply decoupling to achieve the best results when using the ds4302, decouple the power supply with a 0.01? or a 0.1? capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as pos- sible to the v cc and gnd pins of the ds4302 to mini- mize lead inductance. sda and scl pullup resistors pullup resistor values for sda and scl should be cho- sen to ensure that the rise and fall times listed in the ac electrical characteristics are within specification. pac ka ge information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip information transistor count: 2428 substrate connected to ground
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs ds4302 part number table notes: see the ds4302 quickview data sheet for further information on this product family or download the ds4302 full data sheet (pdf, 544kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number notes free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds4302z-020+ 20kohms soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+2 * 0c to +70c rohs/lead-free: yes materials analysis ds4302z-020+t&r 20kohms soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+2 * 0c to +70c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y
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